• DocumentCode
    1811825
  • Title

    A don´t-care based image circuit for function verification

  • Author

    Rau, J.C. ; Chen, Y.M. ; Chang, S.C.

  • Author_Institution
    Dept. of Electr. Eng., Tamkang Univ., Taipei, Taiwan
  • Volume
    5
  • fYear
    2002
  • fDate
    2002
  • Abstract
    In this paper, we propose a novel way to build a "DC_image" circuit for the don\´t cares. The DC_image circuits are concatenated with the inputs of the two circuits under verification. By adding the image circuits, no matter how don\´t cares are in on-/off-sets, we can directly verify the two circuits with DC_image circuits and claim whether there exists an inconsistency between the original and optimized circuits. Our experimental results show that by the DC_image circuits, the verification process can be sped up tremendously.
  • Keywords
    circuit optimisation; formal verification; logic testing; concatenated circuits; don´t-care based image circuit; equivalence checking; function verification; optimized circuits; serial cube chain don´t-care image circuits; Automatic test pattern generation; Binary decision diagrams; Boolean functions; Central Processing Unit; Circuits; Computer science; Concatenated codes; DC generators; Data structures; NP-complete problem;
  • fLanguage
    English
  • Publisher
    ieee
  • Conference_Titel
    Circuits and Systems, 2002. ISCAS 2002. IEEE International Symposium on
  • Print_ISBN
    0-7803-7448-7
  • Type

    conf

  • DOI
    10.1109/ISCAS.2002.1010706
  • Filename
    1010706