A 3.4-mW 128-MHz analog correlator for DS-CDMA wireless applications

Author

Eltokhy, Mostafa A R ; Tan, Boon-Keat ; Matsuoka, Toshimasa ; Taniguchi, Kenji

Author_Institution

Dept. of Electron. & Inf. Syst., Osaka Univ., Japan

Volume

5

fYear

2002

fDate

2002

Abstract

A new analog correlator circuit for a direct sequence code division multiple access (DS-CDMA) demodulator is proposed. The circuit consists of only 13 switches, 4 capacitors and 2 level shifters. Simulation with a code length of 127 reveals that the proposed circuit dissipates 3.4 mW at 128 MHz. The proposed circuit had been implemented into a Si chip using a 0.6 μm CMOS process. The occupation area of 256 μm×245 μm is estimated to be 9 times smaller compared to other reported equivalent analog correlators.

Keywords

CMOS analogue integrated circuits; VLSI; analogue processing circuits; code division multiple access; correlators; elemental semiconductors; mobile radio; radio receivers; silicon; spread spectrum communication; 0.6 micron; 128 MHz; 245 micron; 256 micron; 3.4 mW; CMOS process; DS-CDMA demodulator; Si; Si chip; VLSI implementation; analog correlator circuit; direct sequence CDMA; direct sequence code division multiple access; Capacitors; Circuits; Clocks; Correlators; Demodulation; Direct-sequence code-division multiple access; Multiaccess communication; Sampling methods; Switches; Transmitters;

fLanguage

English

Publisher

ieee

Conference_Titel

Circuits and Systems, 2002. ISCAS 2002. IEEE International Symposium on

Print_ISBN

0-7803-7448-7

Type

conf

DOI

10.1109/ISCAS.2002.1010719

Filename

1010719