Title :
High performance Al dual damascene process with elevated double stoppers
Author :
Nakamura, N. ; Anand, M.B. ; Wada, J. ; Oikawa, Y. ; Katata, T. ; Shiba, K. ; Shibata, H.
Author_Institution :
Toshiba Corp., Yokohama, Japan
Abstract :
An integrated Al dual damascene process which can simultaneously realize smaller interconnect wire resistance variations and reduced wire-to-wire capacitance increase is presented. The main feature of the process is using SiN etch stoppers which are well removed from the corners of the wires. Compared to the conventional damascene structure with SiN etch stoppers directly above and below the wires, the wire-to-wire capacitance increase due to the presence of SiN is reduced by half in the new process. By integrating the process with a newly developed low resistance Al reflow sputter process using a Nb liner, it is confirmed that excellent electrical characteristics are obtained for the dual-damascene wires and vias
Keywords :
aluminium; capacitance; electric resistance; etching; integrated circuit interconnections; integrated circuit metallisation; silicon compounds; sputter deposition; surface treatment; Al dual damascene process; Al-Nb; Al-SiN; Nb liner; SiN etch stoppers; damascene structure; dual-damascene vias; dual-damascene wires; electrical characteristics; elevated double stoppers; integrated Al dual damascene process; interconnect wire resistance variations; low resistance Al reflow sputter process; wire-to-wire capacitance; Atomic measurements; Capacitance; Costs; Dielectric constant; Etching; Fabrication; Force measurement; Niobium; Silicon compounds; Wires;
Conference_Titel :
Interconnect Technology Conference, 1998. Proceedings of the IEEE 1998 International
Conference_Location :
San Francisco, CA
Print_ISBN :
0-7803-4285-2
DOI :
10.1109/IITC.1998.704774