VHDL modeling and simulation of the back-propagation algorithm and its mapping to the RM

The Reconfigurable Machine (RM) is a parallel architecture that is built using Xilinx´s 4005 field programmable gate array (FPGA) and associated fast static random-access memories (SRAMs). VHDL modeling and simulation of a fully connected three-layer back-propagation (BP) are attempted in the present work with a view towards its mapping to a reconfigurable parallel architecture. The mapping encompasses both the forward and backward passes. A bottom-up approach is used which starts from the configuration of processing elements to achieve effective computation of floating-point sum-of-products. The FPGAs perform the floating-point multiplication, addition, and function evaluation, while the local SRAMs are used for storing input/output (I/O) data for the RM