Title :
3D scheduling based on code space exploration for dynamically reconfigurable systems
Author :
Kaneko, Mineo ; Yokoyama, Jun´ichi ; Tayu, Satoshi
Author_Institution :
Graduate Sch. of Inf., Japan Adv. Inst. of Sci. & Technol., Ishikawa, Japan
Abstract :
This paper treats scheduling tasks on a dynamically and partly reconfigurable device. We propose a coding scheme which represents both temporal schedule of module reconfigurations and task executions and spatial placement of reconfigured modules. Registers for transferring data between tasks are also considered as run-time configured modules, and the highlight of the proposed coding scheme is the mechanism to guarantee nonoverlapping between 3D (spatial×temporal) life-durations of different objects and temporal overlapping between some pairs of modules to complete data transfer. As a design method to optimize schedule on a dynamically and partly reconfigurable device, simulated annealing (SA) based exploration of the solution space constructed by our coding scheme is demonstrated.
Keywords :
VLSI; modules; reconfigurable architectures; scheduling; simulated annealing; 3D scheduling; code space exploration; data transfer; dynamically reconfigurable systems; nonoverlapping; partly reconfigurable device; reconfigured modules; run-time configured modules; simulated annealing; solution space; spatial placement; temporal schedule; Dynamic scheduling; Hardware; Information science; Partitioning algorithms; Processor scheduling; Registers; Scheduling algorithm; Simulated annealing; Space exploration; Space technology;
Conference_Titel :
Circuits and Systems, 2002. ISCAS 2002. IEEE International Symposium on
Print_ISBN :
0-7803-7448-7
DOI :
10.1109/ISCAS.2002.1010741