Copper dual damascene wiring for sub-0.25 μm CMOS technology

Author

Heidenreich, J. ; Edelstein, D. ; Goldblatt, R. ; Cote, W. ; Uzoh, C. ; Lustig, N. ; McDevitt, T. ; Stamper, A. ; Simon, A. ; Dukovic, J. ; Andricacos, P. ; Wachnik, R. ; Rathore, H. ; Katsetos, T. ; McLaughlin, P. ; Luce, S. ; Slattery, J.

Author_Institution

IBM Corp., Hopewell Junction, NY, USA

fYear

1998

fDate

1-3 Jun 1998

Firstpage

151

Lastpage

153

Abstract

Recently, IBM announced the implementation of a full copper interconnect scheme which will be manufactured on its high-performance 0.20 μm CMOS products later this year. Features of this technology are presented here, as well as functional verification on CMOS chips. To reach this level, extensive yield, reliability, and stress testing had to be done on test and product-like chips, including those packaged into product modules. Data is presented from this testing, ranging from experiments designed to promote copper contamination of the MOS devices, to functional stressing of packaged SRAM modules. A fully-functional high-performance microprocessor with 6 levels of Cu wiring has also been demonstrated. The results in all areas are equal to or better than standards set by our current Al(Cu) wiring technology. This work demonstrates that the potential problems associated with copper wiring can be overcome to produce reliable and properly-functioning ULSI CMOS chips with a cost-effective, extendible process

Keywords

CMOS integrated circuits; SRAM chips; ULSI; copper; integrated circuit interconnections; integrated circuit metallisation; integrated circuit reliability; integrated circuit testing; integrated circuit yield; microprocessor chips; surface contamination; 0.2 micron; 0.25 micron; CMOS chips; CMOS products; CMOS technology; Cu; Cu wiring; MOS devices; ULSI CMOS chips; copper contamination; copper dual damascene wiring; copper interconnect scheme; copper wiring; cost-effective process; extendible process; functional stressing; functional verification; microprocessor; packaged SRAM modules; packaged chips; product modules; product-like chips; reliability testing; stress testing; test chips; yield testing; CMOS technology; Contamination; Copper; MOS devices; Manufacturing; Packaging; Random access memory; Stress; Testing; Wiring;

fLanguage

English

Publisher

ieee

Conference_Titel

Interconnect Technology Conference, 1998. Proceedings of the IEEE 1998 International

Conference_Location

San Francisco, CA

Print_ISBN

0-7803-4285-2

Type

conf

DOI

10.1109/IITC.1998.704776

Filename

704776