DocumentCode
181283
Title
Impact of grounding the bottom oxide protection layer on the short-circuit ruggedness of 4H-SiC trench MOSFETs
Author
Tanaka, Ryo ; Kagawa, Yasuhiro ; Fujiwara, N. ; Sugawara, Kenji ; Fukui, Yasuhito ; Miura, Naruhisa ; Imaizumi, Masayuki ; Yamakawa, Satoshi
Author_Institution
Adv. Technol. R&D Center, Mitsubishi Electr. Corp., Amagasaki, Japan
fYear
2014
fDate
15-19 June 2014
Firstpage
75
Lastpage
78
Abstract
This paper investigates the effects of grounding the p-type gate-oxide protection layer called bottom p-well (BPW) of a trench-gate SiC-MOSFET on the short-circuit ruggedness of the device. The BPW is grounded by forming ground contacts in various cell layouts, and the layout of the contact cells is found to be a significant factor that determines the short-circuit safe operation area (SCSOA) of a device. By grounding the BPW in an optimized cell layout, an SCSOA of over 10 μs is obtained at room temperature. Further investigation revealed that minimizing the distance between the ground contacts for the BPW is a key to developing a highly-robust, high-performance power device.
Keywords
MOSFET; earthing; short-circuit currents; silicon compounds; wide band gap semiconductors; 4H-SiC trench MOSFETs; BPW; H-SiC; SCSOA; bottom oxide protection layer grounding; bottom p-well; contact cells; ground contacts; highly-robust high-performance power device; optimized cell layout; p-type gate-oxide protection layer; short-circuit ruggedness; short-circuit safe operation area; temperature 293 K to 298 K; trench-gate SiC-MOSFET; Contacts; Grounding; Lattices; Layout; Logic gates; Performance evaluation; Resistance;
fLanguage
English
Publisher
ieee
Conference_Titel
Power Semiconductor Devices & IC's (ISPSD), 2014 IEEE 26th International Symposium on
Conference_Location
Waikoloa, HI
ISSN
1943-653X
Print_ISBN
978-1-4799-2917-7
Type
conf
DOI
10.1109/ISPSD.2014.6855979
Filename
6855979
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