CVD Cu process integration for sub-0.25 μm technologies

Author

Zhang, Jiming ; Denning, Dean ; Braeckelmann, Greg ; Venkatraman, Ram ; Fiordalice, Robert ; Weitzman, E.

Author_Institution

Adv. Products Res. & Dev. Lab., Motorola Inc., Austin, TX, USA

fYear

1998

fDate

1-3 Jun 1998

Firstpage

163

Lastpage

165

Abstract

This paper discusses CVD Cu process development and back-end dual-inlaid integration of CVD Cu on sub-0.25 μm device structure. CVD Cu was deposited on a variety of barriers, including CVD TiN, PVD Ta, PVD TaN and a hybrid barrier, using a direct liquid delivery (DLI) system. Excellent step coverage and via/trench filling were observed. Low sheet resistivity and low contact resistance have been obtained through a CVD/PVD reflow process using CVD TiN and hybrid barriers. The extendability of the CVD Cu based process technology is also discussed

Keywords

chemical interdiffusion; chemical vapour deposition; contact resistance; copper; diffusion barriers; electrical resistivity; integrated circuit interconnections; integrated circuit metallisation; integrated circuit testing; 0.25 micron; CVD Cu; CVD Cu based process technology; CVD Cu process development; CVD Cu process integration; CVD TiN barrier; CVD/PVD reflow process; Cu; Cu-Ta; Cu-TaN; Cu-TiN; DLI direct liquid delivery system; PVD Ta barrier; PVD TaN barrier; Ta; TaN; TiN; back-end dual-inlaid integration; barrier layers; contact resistance; device structure; hybrid barrier; sheet resistivity; step coverage; trench filling; via filling; Annealing; Atherosclerosis; Conductivity; Contact resistance; Copper; Etching; Fluid flow; Plasma temperature; Research and development; Tin;

fLanguage

English

Publisher

ieee

Conference_Titel

Interconnect Technology Conference, 1998. Proceedings of the IEEE 1998 International

Conference_Location

San Francisco, CA

Print_ISBN

0-7803-4285-2

Type

conf

DOI

10.1109/IITC.1998.704780

Filename

704780