Title :
Correlation of film thickness and deposition temperature with PAI and the scalability of Ti-salicide technology to sub-0.18 μm regime
Author :
Ho, C.S. ; Karunasiri, R. IP G ; Chua, S.J. ; Pey, K.L. ; Siah, S.Y. ; Lee, K.H. ; Chan, L.H.
Author_Institution :
Dept. of Electr. Eng., Nat. Univ. of Singapore, Singapore
Abstract :
We present the first working solutions for a sub-0.25 μm Ti-salicide process incorporating 14Si or Ar+ PAI (preamorphization implant). Various film stack thicknesses, collimated deposition temperatures, and key PAI process parameters are studied and evaluated. The use of high-temperature PVD with PAI is emphasized to yield devices with low gate sheet resistance and tight leakage distributions
Keywords :
amorphisation; doping profiles; electric resistance; integrated circuit interconnections; integrated circuit metallisation; ion implantation; leakage currents; sputter deposition; thermal analysis; titanium compounds; 0.18 micron; 0.25 micron; Ar preamorphization implant; PAI; PAI process parameters; Si preamorphization implant; Ti-salicide process; Ti-salicide technology; TiSi2:Ar; TiSi2:Si; collimated deposition temperature; deposition temperature; film stack thickness; film thickness; gate sheet resistance; high-temperature PVD; leakage distribution; scalability; Annealing; Argon; Atherosclerosis; Collimators; Electrical resistance measurement; Implants; Manufacturing processes; Scalability; Temperature; Tin;
Conference_Titel :
Interconnect Technology Conference, 1998. Proceedings of the IEEE 1998 International
Conference_Location :
San Francisco, CA
Print_ISBN :
0-7803-4285-2
DOI :
10.1109/IITC.1998.704789
