Interconnect material and CMP process change effects on local interconnect planarity

Author

Mendonca, J. ; Dang, C. ; Pettinato, C. ; Cope, J. ; Garcia, H. ; Saravia, J. ; Farkas, J. ; Watts, D. ; Klein, J.

Author_Institution

Adv. Products Res. & Dev. Lab., Motorola Inc., Austin, TX, USA

fYear

1998

fDate

1-3 Jun 1998

Firstpage

196

Lastpage

198

Abstract

With finer geometries and multiple metal levels, CMP planarity demands have increased at the lower device levels. Interconnect material changes (metals such as W, Ti, TiN and dielectrics such as BP-TEOS, HDP, and F-HDP) and CMP process changes (such as pads and tool sets) were explored to improve the post-polish planarity at the local interconnect level. The pad hardness was found to offer the best avenue, with up to a tenfold decrease in the post-CMP interlevel dielectric thickness range

Keywords

chemical interdiffusion; chemical mechanical polishing; dielectric thin films; diffusion barriers; hardness; integrated circuit interconnections; integrated circuit metallisation; integrated circuit testing; surface topography; BP-TEOS dielectrics; CMP pads; CMP planarity; CMP process; CMP tool sets; F-HDP dielectrics; HDP dielectrics; IC geometry; Ti metallization; TiN metallization; W metallization; W-Ti-SiO₂; W-TiN-Ti-SiO₂; interconnect dielectrics; interconnect material; interconnect metals; local interconnect planarity; multiple metal levels; pad hardness; post-CMP interlevel dielectric thickness; post-polish planarity; Dielectric materials; Electrical resistance measurement; Etching; Geometry; Inorganic materials; Laboratories; Monitoring; Process control; Research and development; Tin;

fLanguage

English

Publisher

ieee

Conference_Titel

Interconnect Technology Conference, 1998. Proceedings of the IEEE 1998 International

Conference_Location

San Francisco, CA

Print_ISBN

0-7803-4285-2

Type

conf

DOI

10.1109/IITC.1998.704790

Filename

704790