Title :
FPA10-A 4 MFLOP floating point coprocessor for ARM
Author :
Harrod, P.L. ; Baum, A.J. ; Biggs, J.P. ; Howard, D.W. ; Merritt, A.J. ; Oldham, H.E. ; Seal, D.J. ; Watters, H.L.
Author_Institution :
Advanced RISC Machines Ltd., Cambridge, UK
Abstract :
The FPA10 has been designed to provide balanced floating point performance to complement the integer performance of ARM CPUs (central processing units) while remaining a low-cost and low-power device. Concurrent load/store and arithmetic execution units, speculative execution, and innovative circuit design enable 4 MFLOPS to be achieved with a power dissipation of 250 mW at 5 V. The 134K transistor, 66.7-mm 2 chip is implemented in 1-μm CMOS and is packaged in a low-cost 68-pin PLCC. FPA 10 implements a subset of the ARM floating-point instruction set; other, rarely executed instructions and most exception conditions are handled by software emulation. This has enabled a low-power, low-cost design which provides floating-point performance that is well-matched with the ARM integer performance
Keywords :
floating point arithmetic; 4 MFLOPS; 5 V; ARM CPU; ASIC; CMOS; FPA10; PLCC; RISC CPU; floating point coprocessor; four-stage pipeline; full custom design; integer performance; low-cost; low-power; speculative execution; standard cell; Arithmetic; Central Processing Unit; Coprocessors; Costs; Frequency; Hardware; Pipeline processing; Power dissipation; Reduced instruction set computing; Seals;
Conference_Titel :
Custom Integrated Circuits Conference, 1993., Proceedings of the IEEE 1993
Conference_Location :
San Diego, CA
Print_ISBN :
0-7803-0826-3
DOI :
10.1109/CICC.1993.590407
