Title :
Efficient VLSI architectures of lifting-based discrete wavelet transform by systematic design method
Author :
Huang, Chao-Tsung ; Tseng, Po-Chih ; Chen, Liang-Gee
Author_Institution :
DSP/IC Design Lab, Nat. Taiwan Univ., Taipei, Taiwan
Abstract :
In this paper, an effective systematic design method is proposed to construct several efficient VLSI architectures of 1-D and 2-D lifting-based discrete wavelet transform. This design method first performs a specific lifting factorization for any finite discrete wavelet transform filter to obtain an optimal algorithm representation for hardware implementation. The optimized algorithm then turns into 1-D systolic architectures through dependence graph formation and systolic arrays mapping. Based on the 1-D architectures, a general 2-D discrete wavelet transform framework is used to construct the corresponding 2-D architectures. According to the comparison results, the constructed VLSI architectures are more efficient than previous arts in term of arithmetic units and memory storage.
Keywords :
VLSI; channel bank filters; digital filters; discrete wavelet transforms; integrated circuit design; linear phase filters; matrix decomposition; signal reconstruction; systolic arrays; (9,7) odd symmetric biorthogonal filter; 1-D systolic architectures; arithmetic units; dependence graph formation; efficient VLSI architectures; finite discrete wavelet transform filter; general 2-D discrete wavelet transform framework; lifting-based discrete wavelet transform; linear phase filter banks; memory storage; optimal algorithm representation; specific lifting factorization; systematic design method; systolic array mapping; Design methodology; Discrete cosine transforms; Discrete transforms; Discrete wavelet transforms; Filters; Image coding; Matrix decomposition; Very large scale integration; Wavelet analysis; Wavelet transforms;
Conference_Titel :
Circuits and Systems, 2002. ISCAS 2002. IEEE International Symposium on
Print_ISBN :
0-7803-7448-7
DOI :
10.1109/ISCAS.2002.1010766