Title :
Design of full adder/subtractor using irreversible IG-A gate
Author :
Chowdhury, Adib Kabir ; Tan, Daniel Yong Wen ; Yew, Simon Lau Boung ; Wyai, Gary Loh Chee ; Madon, Bakri ; Thangarajah, Akilan
Author_Institution :
Sch. of Comput., Univ. Coll. Technol. Sarawak, Sibu, Malaysia
Abstract :
In recent years, reversible computation has received much attention in the field of low power circuit design. In this paper, an irreversible IG-A gate is presented. The gate is further used to design irreversible full adder/subtractor (IAS). Furthermore, IAS block is utilized to construct n-bit adder and subtractor. Proposed IAS design is analyzed and compared against the existing reversible methods. Features such as, hardware cost, logic calculation and gate count are investigated to show the efficiency of the design. Transistor level design and simulation of IG-A circuit are shown using Cadence OrCAD Lite. The one-bit IAS simulation results are verified using Altera Quartus II and ModelSim software. Simulation results show that the circuit offers reduced hardware complexity as compared to the existing reversible full adder design.
Keywords :
adders; circuit simulation; logic design; logic gates; low-power electronics; network synthesis; Altera Quartus II; Cadence OrCAD Lite; IAS block; IG-A circuit simulation; ModelSim software; irreversible IG-A gate; irreversible full adder; irreversible full subtractor; low power circuit design; n-bit adder; n-bit subtractor; one-bit IAS simulation; reversible computation; transistor level design; Adders; Hardware; Integrated circuit modeling; Inverters; Logic gates; Simulation; Transistors; full adder/subtractor; hardware complexity; irreversible; logic calculation; reversible logic; transistor;
Conference_Titel :
Computer, Communications, and Control Technology (I4CT), 2015 International Conference on
Conference_Location :
Kuching
DOI :
10.1109/I4CT.2015.7219546
