Techniques to improve linearity of CMOS sample-and-hold circuits for achieving 100 dB performance at 80 MSps

Sample and hold circuits (SHC) form the front-end circuitry for the switched capacitance pipeline or successive approximation register A/D converter (ADC). The linearity obtained from SHC directly impacts the overall linearity obtainable from the A/D converter. In this paper we describe a new technique for the input-sampling network. Open loop gain and settling time have been optimized for maximum linearity. We also propose a novel architecture to resolve the closed loop pole-zero problems. Linearity as high as 100 dB at a clock speed of 80 MHz was achieved.