A programmable clock generator with 50 to 350 MHz lock range for video signal processors

Author

Goto, Junichi ; Yamashina, Masakazu ; Inoue, Toshiaki ; Shih, Benjamin S. ; Koseki, Youichi ; Horiuchi, Tadahiko ; Hamatake, Nobuhisa ; Kumagai, Kazuyoshi ; Enomoto, Tadayoshi ; Yamada, Hachiro

Author_Institution

NEC Corp., Sagamihara, Kanagawa, Japan

fYear

1993

fDate

9-12 May 1993

Abstract

Using 0.5-μm CMOS triple-layer Al technology, a programmable clock generator based on a PLL (phase-locked loop) circuit has been developed for use as an on-chip clock generator in a 300-MHz video signal processor. It generates an internal clock whose frequency is an integral multiple of an external clock frequency, and its oscillating frequency ranges from 50 to 350 MHz. Experimental results show that the clock generator generates a 297-MHz clock with jitter reduced to 180 ps with a 27-MHz input clock, and that it oscillates at up to 348 MHz with a 31.7-MHz input clock

Keywords

digital phase locked loops; 0.5 micron; 50 to 350 MHz; ASIC; CMOS triple-layer Al technology; PLL; frequency multiplier; on-chip clock generator; oscillating frequency; programmable clock generator; reduced jitter; video signal processors; CMOS technology; Charge pumps; Clocks; Filters; Phase frequency detector; Phase locked loops; Power supplies; Signal generators; Signal processing; Voltage-controlled oscillators;

fLanguage

English

Publisher

ieee

Conference_Titel

Custom Integrated Circuits Conference, 1993., Proceedings of the IEEE 1993

Conference_Location

San Diego, CA

Print_ISBN

0-7803-0826-3

Type

conf

DOI

10.1109/CICC.1993.590474

Filename

590474