Title :
A low power trainable analogue neural network classifier chip
Author :
Leong, Philip H W ; Jabri, Marwan A.
Author_Institution :
Electr. Eng., Sydney Univ., Australia
Abstract :
The authors describe an analogue VLSI chip called Kakadu which implements a trainable (10, 6, 4) multilayer perceptron. Kakadu is a classifier designed for low-power applications and has a typical power consumption of 20 μW. It was tested on many classification problems, including XOR, 4-b parity, character recognition, and arrhythmia classification
Keywords :
neural chips; 20 muW; Kakadu; MATIC algorithm; XOR; analogue VLSI chip; analogue neural network classifier chip; arrhythmia classification; character recognition; low power trainable; low-power; multilayer perceptron; parity; power consumption; Artificial neural networks; Australia; Character recognition; Circuit testing; Computer architecture; Energy consumption; Neural networks; Neurons; Resistors; Very large scale integration;
Conference_Titel :
Custom Integrated Circuits Conference, 1993., Proceedings of the IEEE 1993
Conference_Location :
San Diego, CA
Print_ISBN :
0-7803-0826-3
DOI :
10.1109/CICC.1993.590475
