Title :
A VLSI array processor for neural network algorithms
Author :
Beichter, J. ; Brüls, N. ; Ramacher, U. ; Sicheneder, E. ; Klar, H.
Author_Institution :
Siemens AG, Munich, Germany
Abstract :
A chip based on a new scalable parallel systolic VLSI architecture is presented for executing the compute-bound algorithmic primitives used by search and learning algorithms in neural networks and low-level signal processing. The architecture combines high performance with a high grade of flexibility for all types and sizes of neural networks. The processor chip can be connected to form 1-D and 2-D arrays. By offering an accuracy of 16 b for input and 47 b for output data, the chip achieves 800M connections/s at 50 MHz. It is realized in 1.0-μm CMOS (610K transistors on 13.7 × 13.7 mm2) and has a total data bandwidth of 10.9 Gb/s
Keywords :
neural chips; 1 micron; 1-D arrays; 10.9 Gbit/s; 2-D arrays; 50 MHz; CMOS; VLSI array processor; compute-bound algorithmic primitives; high performance; low-level signal processing; neural network algorithms; scalable parallel systolic VLSI architecture; search and learning algorithms; Adders; Computer architecture; Computer networks; Distributed computing; Joining processes; Neural networks; Parallel processing; Silicon; Statistics; Very large scale integration;
Conference_Titel :
Custom Integrated Circuits Conference, 1993., Proceedings of the IEEE 1993
Conference_Location :
San Diego, CA
Print_ISBN :
0-7803-0826-3
DOI :
10.1109/CICC.1993.590476