Performance evaluation of the UHF class 0 RFID tag for the proposed anti-collision algorithm

The Radio Frequency Identification (RFID) system is an automatic identification technology of choice over other existing technologies. Nowadays, the ability to identify many objects simultaneously is crucial for more advanced applications such as to identify objects in the warehouse and at the supermarket. These applications require an efficient identification technique which can identify many objects at one time without long delay. Meanwhile, one of the main issues during the identification process is the tags collision which occurs when all these tags are simultaneously responding to the reader commands. The RFID applications also require the tag to be simple, small, cheap and memoryless. Therefore the research is to evaluate the the performance of the proposed tag architecture for the Fast Detection Anti-collision Algorithm (FDACA) using the Total Tag Replies parameter. The Total Tag Replies parameter for the Binary Tree and the proposed FDACA tags are explained. The tag architecture for both techniques are described in Verilog Hardware Description Language (HDL) and simulated using Xilinix software. Then both tag architectures are synthesized using Application Specific Integrated Circuit (ASIC) technology (0.18 μm Library, Synopsys Compiler and tools). The tags performances are evaluated based on the obtained synthesis parameters.