A high level synthesis interface to erasable programmable logic devices

A high-level synthesis tool for erasable programmable logic devices is described. The intended use of this tool is rapid prototyping of custom designs. Unlike existing synthesis tools for field programmable logic devices, which perform Boolean-level minimization only, this tool performs the high-level synthesis tasks of scheduling, allocation, resource sharing, and binding. The advantage of this approach is that the same Verilog input description and the same synthesis tool are used to synthesize both the custom design and the prototype, thereby guaranteeing consistency. This tool has been tested on several design examples and verified via simulation and working programmed parts to match the behavioral specification