Roadmap towards ultimately-efficient zeta-scale datacenters

Communication via narrow busses on large printed circuit boards slowed the efficiency improvements for PCs and servers causing increased power consumption. Low-power microservers continued to shrink reaching better efficiency. The focus on transistor scaling opened a communication bandwidth and latency gap and created two major roadblocks to further progress: power density and communication delays between processors and memory or other processors. With growing system sizes, spatial and temporal communication requires larger fractions of the overall system resources. The transition from 2-D scaling to 3-D integration offers an excellent opportunity to improve computer density and efficiency. Interlayer cooled chip stacks allow the integration of several logic layers each with massive amounts of main memory [1]. These systems use 3D communication and ultra-compact cooling similar to a human brain. We explore how brain-inspired bionic packaging concepts can be transferred to future 3-D computers to eliminate current bottlenecks. To finally reach human level performance and efficiency computer design needs to undergo several major paradigm changes.