Advantages of heterogeneous logic block architecture for FPGAs

The authors consider field programmable gate arrays (FPGAs) that use two different sizes of lookup table (LUT) logic blocks and investigate the area-efficiency of different mixtures of different sizes of LUTs. Experimental results on a set of benchmark circuits indicate that several heterogeneous architectures achieve significant reduction in the number of programming bits and logic block pins compared to the industry standard 4-input LUTs. A 6-LUT/4-LUT combination will likely exhibit better performance with nearly equivalent area than a homogeneous 4-LUT FPGA