A buffer size customization approach for application-specific NoC design

In this paper, we present a design space exploration framework to allow the designer to customize a candidate on-chip interconnect architecture in order to match the application-specific workload in System-on-Chip. To show the benefit of using this methodology, a buffer space allocation algorithm is presented to allow designers to allocate only the required resource for each channel based on the traffic pattern of a target application. Simulations are conducted and results show that the proposed method achieves similar performance compared to the uniformly buffer space allocation method while using only 70% of resources budget.