Title :
Macromodeling BiCMOS gates for circuit optimization
Author :
Chen, D.-P. ; Zukowski, C. ; Banu, M.
Author_Institution :
AT&T Bell Lab., Murray Hill, NJ, USA
Abstract :
The authors present a simple BiCMOS analytical delay formula, including high-level injection effects, and a table-lookup method for finding the optimal size ratio of MOS and bipolar transistors of a BiCMOS logic gate. Experimental results of their application in a circuit optimizer called the family mixing optimizer (FMO) are shown. Based on these approaches, the circuit optimizer can easily estimate delays and adjust transistor sizes, and quickly find most of the basic optimizations that can be made
Keywords :
BiCMOS logic circuits; BiCMOS gates; circuit optimization; delay formula; family mixing optimizer; high-level injection effects; logic gate; macromodelling; optimal size ratio; table-lookup method; transistor sizes; BiCMOS integrated circuits; Bipolar transistors; Capacitance; Circuit optimization; Delay effects; Frequency estimation; Inverters; Logic gates; MOSFETs; Transconductance;
Conference_Titel :
Custom Integrated Circuits Conference, 1993., Proceedings of the IEEE 1993
Conference_Location :
San Diego, CA
Print_ISBN :
0-7803-0826-3
DOI :
10.1109/CICC.1993.590582
