An efficient macromodel for static CMOS multi-port memories

The modelling and design of a six-port CMOS static RAM are described. Due to minimum area constraints imposed by the wiring matrix necessary for addressing, local interconnect, etc. the cell is relatively large; but, as a result, the cell can swing the bit line extremely quickly. The memory system, which is a true multi-port memory system, can be read and written to independently and simultaneously, subject to consistency constraints. A detailed circuit analysis and SPICE circuit simulations of the circuit extracted from a custom layout are presented