Title :
Modifying the netlist after placement for performance improvement
Author :
Ginetti, Arnold ; Brasen, Daniel
Author_Institution :
Compass Design Autom., Antipolis, France
Abstract :
A postplacement netlist modifier which improves the performance of a placed netlist is presented. Iterative technology remapping operations customize the most critical path timing for physical wire capacitances that are unique to a standard-cell placement. The improvement is reached through three operations: buffer tree resynthesis, gate drive resizing, and gate reconnection. Results show up to a 13% reduction in circuit timing for MCNC benchmarks that have already been optimized at the logic level for timing
Keywords :
circuit layout CAD; ASIC; MCNC benchmarks; buffer tree resynthesis; circuit timing; critical path timing; gate drive resizing; gate reconnection; iterative technology remapping; logic synthesis; performance improvement; physical wire capacitances; postplacement netlist modifier; standard-cell placement; Boolean functions; Capacitance; Circuit synthesis; Delay; Design automation; Equations; Integrated circuit interconnections; Logic; Timing; Wire;
Conference_Titel :
Custom Integrated Circuits Conference, 1993., Proceedings of the IEEE 1993
Conference_Location :
San Diego, CA
Print_ISBN :
0-7803-0826-3
DOI :
10.1109/CICC.1993.590590
