Title :
A 30 GS/s 4-Bit Binary Weighted DAC in SiGe BiCMOS Technology
Author :
Halder, Sebastian ; Gustat, H.
Author_Institution :
IHP Frankfurt, Frankfurt
fDate :
Sept. 30 2007-Oct. 2 2007
Abstract :
This paper presents a 4-bit 30 GS/S binary weighted DAC in 0.25 mum BiCMOS technology. The binary weighting function was implemented in the load resistor instead of the current sources. This DAC showed 0.49 LSB and 0.57 LSB of INL and DNL respectively. 0.92 pJ FOM was achieved with 3.5V of power supply at a conversion rate of 30 GHz.
Keywords :
BiCMOS integrated circuits; digital-analogue conversion; FOM; SiGe BiCMOS technology; binary weighted DAC; digital-analogue converter; figure-of merit; frequency 30 GHz; load resistor; size 0.25 mum; voltage 3.5 V; word length 4 bit; BiCMOS integrated circuits; Germanium silicon alloys; Laser radar; Linearity; Phase locked loops; Resistors; Sampling methods; Signal synthesis; Silicon germanium; Switches; Bipolar circuit; current steering DAC; high-speed logic; resistive weighting; unary weighted architecture;
Conference_Titel :
Bipolar/BiCMOS Circuits and Technology Meeting, 2007. BCTM '07. IEEE
Conference_Location :
Boston, MA
Print_ISBN :
978-1-4244-1018-7
DOI :
10.1109/BIPOL.2007.4351836
