Performance analysis of reduced complexity Wallace multiplier using energy efficient CMOS full adder

Most fast computing applications required some arithmetic modules Multiplier is one of the most important module in such applications. Multipliers and their associated circuits like half adders, full adders and accumulators consume a significant portion of most high speed applications. Therefore, it is necessary to increase their performance as well as size efficiency by customization. In order to reduce the hardware which ultimately reduces an area and power, Energy Efficient full adders plays an important role in Wallace tree multiplier. Reduced Complexity Wallace multiplier (RCWM) will have fewer adders than Standard Wallace multiplier (SWM). A Reduced Complexity Wallace multiplier presented in this paper is having the same delay as that of Normal Wallace multipliers. The Reduced complexity reduction method greatly reduces the number of half adders with 75-80% reduction in an area of half adders than standard Wallace multipliers. In both multipliers, at the last stage Carry Propagating Adder (CPA) is used. This paper proposes use of energy efficient CMOS full adder in reduced complexity Wallace Multiplier at the place of Conventional Full adder in order to reduce area, power and improvement in speed.