VLSI suitable synchronization algorithms and architecture for IEEE 802.11a Physical Layer

Author

Schwoerer, Ludwig

Author_Institution

Nokia Res. Center, Bochum, Germany

Volume

5

fYear

2002

fDate

26-29 May 2002

Abstract

A complete modem ASIC has been designed at Nokia Research Center, Bochum, to meet IEEE 802.11 a Physical Layer requirements. This paper gives an overview of the implemented synchronization algorithms, i.e. packet detection, frequency synchronization and fine-timing synchronization. Especially the optimization of these algorithms for an area- and power-efficient design and the resulting architecture are pointed out.

Keywords

IEEE standards; application specific integrated circuits; modems; optimisation; packet radio networks; radio receivers; synchronisation; telecommunication standards; wireless LAN; Bochum; IEEE 802.11 a Physical Layer receiver; Nokia Research Center; VLSI synchronization algorithms; VLSI synchronization architecture; algorithm optimization; area-efficient design; fine-timing synchronization; frequency synchronization; modem ASIC; packet detection; power-efficient design; wireless LAN standard 802.11; Application specific integrated circuits; Channel estimation; Frequency synchronization; Modems; Physical layer; Sampling methods; Sociotechnical systems; Transfer functions; Very large scale integration; Viterbi algorithm;

fLanguage

English

Publisher

ieee

Conference_Titel

Circuits and Systems, 2002. ISCAS 2002. IEEE International Symposium on

Conference_Location

Phoenix-Scottsdale, AZ, USA

Print_ISBN

0-7803-7448-7

Type

conf

DOI

10.1109/ISCAS.2002.1010805

Filename

1010805