Title :
Proposal of 130nm-60V rated fully isolated LDNMOS with double Epi process
Author :
Kwang-Sik Ko ; Sang-Hyun Lee ; Joo-Won Park ; In-Wook Cho ; Kyung-Dong Yoo ; Jong-Hwan Kim
Author_Institution :
Technol. Dev. Team, SK hynix Inc., Cheongju, South Korea
Abstract :
In this paper, we developed 60V rated fully isolated LDNMOS which can be available under negative bias condition. Double epi process for obtaining higher BVdss, PBL (p+ buried layer) for retarding punch through and NBL-2 (n+ buried layer) for a role of electrically connecting NBL-1 are adopted to achieve 60V rated fully isolated LDNMOS. This optimized device has characteristics of Ron.sp 55mohm*mm2 and BVdss 66V. We could also develop 90V rated high side LDMOS with Ron.sp 210mohm*mm2 and BVdss 110V through this same double epi process.
Keywords :
MOSFET; buried layers; power convertors; semiconductor device models; BVdss; NBL-1; NBL-2; PBL; double epi process; fully isolated LDNMOS; n+ buried layer; negative bias condition; p+ buried layer; size 130 nm; voltage 110 V; voltage 60 V; voltage 90 V; Active matrix organic light emitting diodes; Doping; Impact ionization; Inductors; Semiconductor optical amplifiers; Transistors; Transmission line measurements;
Conference_Titel :
Power Semiconductor Devices & IC's (ISPSD), 2014 IEEE 26th International Symposium on
Conference_Location :
Waikoloa, HI
Print_ISBN :
978-1-4799-2917-7
DOI :
10.1109/ISPSD.2014.6856060
