An area-efficient systolic division circuit over GF(2m) for secure communication

We present a novel area-efficient parallel-in parallel-out systolic division circuit (v = a/b) over GF(2^m) based on the extended Stein´s algorithm. By keeping the combined area-time (AT) complexity at the lowest level of O(m²), we evenly distribute the complexity of O(m) in area and time, and design a well-balanced division circuit capable of operating at high speed with high area efficiency. Compared to the other systolic architectures, our design exhibits significant advantages in both area and time.