Title :
Challenges in Cell-Based Design of Very-High-Speed Si-Bipolar IC´s at 100 Gb/s
Author_Institution :
Saarland Univ., Saarbrucken
fDate :
Sept. 30 2007-Oct. 2 2007
Abstract :
A cell-based design concept for higher integrated SiGe-bipolar circuits at 100 Gb/s is presented and discussed with regard to performance limitations. The results of two cell-based designs are demonstrated by a 100 Gb/s 2:1 multiplexer IC and a 100 Gb/s 1:2 demultiplexer IC with on-chip clock-and data-recovery.
Keywords :
bipolar integrated circuits; integrated circuit design; very high speed integrated circuits; SiGe; bit rate 100 Gbit/s; demultiplexer IC; higher integrated SiGe-bipolar circuits; multiplexer IC; on-chip clock-and-data-recovery; very-high-speed Si-bipolar IC; Circuit optimization; Circuit synthesis; Cutoff frequency; Design optimization; Frequency conversion; Germanium silicon alloys; Impedance; Multiplexing; Signal design; Silicon germanium; 100 Gb/s cell-based design; Demultiplexer (DEMUX); Multiplexer (MUX); SiGe bipolar technology; high-speed ICs; high-speed interfaces; impedance mismatch;
Conference_Titel :
Bipolar/BiCMOS Circuits and Technology Meeting, 2007. BCTM '07. IEEE
Conference_Location :
Boston, MA
Print_ISBN :
978-1-4244-1019-4
Electronic_ISBN :
1088-9299
DOI :
10.1109/BIPOL.2007.4351848
