• DocumentCode
    1814571
  • Title

    Efficient algorithms for planar embedding of graphs with constraints in placing specified vertices on face boundaries

  • Author

    Ozawa, Takao

  • Author_Institution
    Dept. of Appl. Math. & Informatics, Ryukoku Univ., Ohtsu, Japan
  • Volume
    5
  • fYear
    2002
  • fDate
    2002
  • Abstract
    As a basis of dealing with various constraints arising in IC layout problems we present efficient algorithms for planar embedding of graphs with constraints on vertices in placing them on face boundaries (=meshes, or windows). The constraints considered are: (1) the specified vertices must be placed on a single face boundary, and (2) the specified vertices must be placed on distinct face boundaries. Our algorithms are based on the vertex addition algorithm and implemented using PQ-trees to achieve linear time and space complexities. Basically, the vertex addition algorithm tests all possible planar embeddings, and thus our algorithms can be modified or extended to deal with wide varieties of constraints.
  • Keywords
    circuit CAD; constraint handling; integrated circuit interconnections; integrated circuit layout; mesh generation; trees (mathematics); IC layout problems; P-nodes; PQ-trees; Q-nodes; distinct face boundaries; face boundary vertex placing constraints; linear space-time complexities; meshes; planar embedding tests; planar graph embedding algorithms; single face boundaries; specified vertices placement; vertex addition algorithm; windows; Circuit testing; Informatics; Integrated circuit layout; Integrated circuit modeling; Joining processes; Mathematics; Planarization; Printed circuits; Semiconductor device modeling; Wires;
  • fLanguage
    English
  • Publisher
    ieee
  • Conference_Titel
    Circuits and Systems, 2002. ISCAS 2002. IEEE International Symposium on
  • Print_ISBN
    0-7803-7448-7
  • Type

    conf

  • DOI
    10.1109/ISCAS.2002.1010812
  • Filename
    1010812