Automatic IP Interface Synthesis Supporting Multi-layer Communication Protocols in SoC Designs

We present an automatic interface synthesis system to expedite the IP (silicon intellectual property) integration process in SoC designs. The concept of multi-layer communication protocols is incorporated into the synthesis process so that interface design targeting different levels of functionality and circuit complexity can be generated automatically. The multi-layered interface architecture template designs are addressed in the first place. We then outline the methodology of interface synthesis, which includes protocol specifications, signal mapping & timing adjustment, interface FSM, and architecture mapping. Interface designs for several benchmark systems are developed using different synthesis options. Besides the advantage of greatly shortened design cycle, the experimental results do show the competitiveness of the automatically generated designs against the manual designs.