DocumentCode :
1814721
Title :
Robust conservative parallel HDL simulation on multi-core CPUs
Author :
Lingfeng Wang ; Hong Chen ; Deng, Yangdong Steve
Author_Institution :
Inst. of Microelectron., Tsinghua Univ., Beijing, China
fYear :
2013
fDate :
1-5 July 2013
Firstpage :
413
Lastpage :
420
Abstract :
Hardware description language (HDL) simulation is the fundamental means of IC verification. The complexity of modern VLSI is constantly posing serious challenges to HDL simulators. We developed a parallel HDL simulation framework in which Verilog HDL is translated into a multithreaded program for parallel execution on an ×86 multi-core processor by following a conservative parallel simulation protocol. We identified two essential problems, deterministic initialization and concurrent memory simulation, which are critical to robust logic simulation. Efficient solutions based on theoretic analysis are proposed to address the problems. Experimental results prove the effectiveness of our simulation framework.
Keywords :
electronic engineering computing; hardware description languages; logic simulation; multi-threading; multiprocessing systems; IC verification; VLSI; Verilog HDL; concurrent memory simulation; conservative parallel simulation protocol; deterministic initialization; hardware description language simulation; multicore CPU; multicore processor; multithreaded program; parallel HDL simulation framework; parallel execution; robust conservative parallel HDL simulation; robust logic simulation; Algorithm design and analysis; Computational modeling; Hardware design languages; Integrated circuit modeling; Protocols; System recovery; Logic simulation; Parallelization of Simulation; conservative simulation; multi-core CPU;
fLanguage :
English
Publisher :
ieee
Conference_Titel :
High Performance Computing and Simulation (HPCS), 2013 International Conference on
Conference_Location :
Helsinki
Print_ISBN :
978-1-4799-0836-3
Type :
conf
DOI :
10.1109/HPCSim.2013.6641448
Filename :
6641448
Link To Document :
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