Title :
Efficient digit-serial normal basis multipliers over GF(2m)
Author :
Reyhani-Masoleh, Arash ; Hasan, M.A.
Author_Institution :
Centre for Appl. Cryptographic Res., Waterloo Univ., Ont., Canada
Abstract :
In this article, two efficient architectures for digit-serial normal basis (DSNB) multipliers over GF(2m) are presented. These two structures have the same gate count and time complexity. A straightforward implementation leaves gate redundancy in both of them. An algorithm which can considerably reduce the redundancy is also developed. Moreover, the proposed architectures are compared with the existing ones in terms of gate and time complexities.
Keywords :
circuit complexity; cryptography; digital arithmetic; logic design; multiplying circuits; redundancy; DSNB multiplier architecture; cryptographic applications; digit-serial normal basis multipliers; finite field arithmetic; gate complexity; gate count; gate redundancy reduction algorithm; time complexity; Arithmetic; Clocks; Delay effects; Elliptic curve cryptography; Elliptic curves; Galois fields; Hardware; Logic; Niobium; Shift registers;
Conference_Titel :
Circuits and Systems, 2002. ISCAS 2002. IEEE International Symposium on
Print_ISBN :
0-7803-7448-7
DOI :
10.1109/ISCAS.2002.1010820
