Title :
A new architecture of RRNS error-correcting QC encoder/decoder and its FPGA implementation
Author :
Wang, Wei ; Swamy, M.N.S. ; Ahmad, M.O.
Author_Institution :
Dept. of Electr. & Comput. Eng., Concordia Univ., Montreal, Que., Canada
Abstract :
In this paper, a new architecture of a redundant residue number system (RRNS) quasi-chaotic (QC) encoder/decoder with an error-correcting ability is proposed for secure communication and is tailored to FPGA implementation. In the proposed architecture, binary subencoders and subdecoders are used so that a number of modulo operations required in the existing design of D. R. Frey (IEEE Trans. Circuits Syst. II, vol. 40, pp. 660-666, Oct. 2000) are replaced by a simple truncation. Furthermore, a size-reduced design of the R/B (residue-to-binary) converter with error-correcting function, which is the crucial part of the system, is proposed. As a case study, the proposed architecture is implemented in FPGA for the case of the 16-bit input and some simulation results obtained.
Keywords :
chaos; codecs; decoding; encoding; error correction; field programmable gate arrays; integrated circuit design; integrated circuit modelling; logic CAD; redundant number systems; residue number systems; telecommunication security; 16 bit; FPGA implementation; QC; R/B converter size-reduction; RRNS; binary subdecoders; binary subencoders; circuit simulation; encoder/decoder architecture; error-correcting function; error-correction; modulo operations; redundant residue number system quasi-chaotic encoder/decoder; residue-to-binary converter; secure communications; truncation; Application specific integrated circuits; Chaotic communication; Computer architecture; Computer errors; Decoding; Equations; Field programmable gate arrays; Filters; Multiaccess communication; Signal processing;
Conference_Titel :
Circuits and Systems, 2002. ISCAS 2002. IEEE International Symposium on
Print_ISBN :
0-7803-7448-7
DOI :
10.1109/ISCAS.2002.1010828
