DocumentCode
1815734
Title
Intel Xeon Phi: Various HPC aspects
Author
Mathur, Kapil ; Agrawal, Sanjay ; Desai, Shaishav ; Malav, Deepti ; Deepu, C.V. ; Misra, Goldi
Author_Institution
HPC Solutions Group, Centre for Dev. of Adv. Comput. (C-DAC), Pune, India
fYear
2013
fDate
1-5 July 2013
Firstpage
688
Lastpage
689
Abstract
Many times enablement of highly parallel applications to deliver very high performance is quite a tough task. This can be because of bottlenecks in the underlying hardware subsystems or overheads imposed by the parallel programming models used. Software development tools play an important role to understand and minimize these bottlenecks. Hence success of an emerging architecture is related to availability of such tools, and support for existing parallel programming models and techniques. Also, computational performance per watt is an important consideration in making the choice of the hardware subsystem. In this poster we have attempted to bring out such HPC aspects of Intel Xeon Phi, a many-core architecture recently launched by Intel.
Keywords
multiprocessing systems; parallel architectures; parallel programming; software tools; HPC aspects; Intel Xeon Phi; computational performance; hardware subsystems; many-core architecture; parallel applications; parallel programming models; software development tools; Computer architecture; Coprocessors; Hidden Markov models; Libraries; Market research; Parallel programming; Scalability;
fLanguage
English
Publisher
ieee
Conference_Titel
High Performance Computing and Simulation (HPCS), 2013 International Conference on
Conference_Location
Helsinki
Print_ISBN
978-1-4799-0836-3
Type
conf
DOI
10.1109/HPCSim.2013.6641495
Filename
6641495
Link To Document