Fast, exploration of ΔΣADC design space

An algorithm used to rapidly evaluate performance of delta-sigma (ΔΣ) analog-to-digital converters (ADC) is presented. The algorithm browses through a set of orders of the converter, numbers of cascaded loops and numbers of bits and decides if a goal dynamic range (DR) can be achieved in a given range of oversampling ratio (OSR) values. The decision of validity of a proposed solution is based on a method to estimate the DR of a converter by Z-domain (polynomial) calculus. The entire design space exploration takes less than 10 minutes of runtime on a 1-GHz computer and is used to select all possible candidates for further (manual or automatic) optimization.