A motion video compression LSI with distributed arithmetic architecture

Author

Tokuno, Yoshio ; Mizutani, Hiroyuki ; Yamazaki, Masato ; Masaki, Hiroshi

Author_Institution

OKI Electric Industry Co., Ltd., Tokyo, Japan

fYear

1993

fDate

9-12 May 1993

Abstract

The authors summarize the algorithm, architecture, and implementation of an LSI that can perform discrete cosine transform (DCT), inverse DCT (IDCT), motion estimation (ME), and video data statistical processing for inter/intra decision (DECISION) at 2.59 GOPS (giga operations per second). This LSI can perform the DCT, IDCT, ME and DECISION in a single chip by switching mode signals. The LSI has a power consumption of 2 W at 40.5-MHz input clock. The chip, designed in a 0.8-μm, double-metal CMOS technology, has 405,000 transistors and a die size of 13.86 × 13.51 mm²

Keywords

video coding; 0.8 micron; 2 W; 40.5 MHz; algorithm; architecture; discrete cosine transform; distributed arithmetic architecture; double-metal CMOS technology; implementation; inter/intra decision; inverse DCT; motion estimation; motion video compression LSI; power consumption; video data statistical processing; Arithmetic; CMOS technology; Circuits; Discrete cosine transforms; Industrial electronics; Large scale integration; Read only memory; Research and development; Very large scale integration; Video compression;

fLanguage

English

Publisher

ieee

Conference_Titel

Custom Integrated Circuits Conference, 1993., Proceedings of the IEEE 1993

Conference_Location

San Diego, CA

Print_ISBN

0-7803-0826-3

Type

conf

DOI

10.1109/CICC.1993.590694

Filename

590694