A single chip multistandard video codec

Author

Bose, Subroto ; Purcell, Steve ; Chiang, Tony

Author_Institution

C-Cube Microsystem, Milpitas, CA, USA

fYear

1993

fDate

9-12 May 1993

Abstract

A programmable chip that implements multiple standards is described. Compliant with ISO MPEG (Moving Pictures Experts Group), it encodes or decodes SIF images at 30 frames/sec. It implements a P × 64 full-duplex CIF codec at 15 frames/sec or QCIF at 30 frames/sec. It contains a glueless 80 Mbyte/sec DRAM (dynamic random-access memory) controller, a 240 MIPS (million instructions per second) SIMD (single instruction, multiple data) processor, and a 2000 MOPS (million operations per second) motion estimator. CCIR 601 video is input with high-quality conversion to SIF format, and a video display controller interpolates to 601 interlaced output

Keywords

ISO standards; 240 MIPS; 80 MByte/s; CCIR 601 video; ISO MPEG; SIF format; SIMD processor; VLSI; full-duplex CIF codec; glueless DRAM controller; high-quality conversion; motion estimator; multiple standards; on-chip coprocessors; programmable chip; single chip multistandard video codec; video display controller; Decoding; Displays; Encoding; Hardware; Motion control; Motion estimation; Random access memory; Video codecs; Video coding; Videoconference;

fLanguage

English

Publisher

ieee

Conference_Titel

Custom Integrated Circuits Conference, 1993., Proceedings of the IEEE 1993

Conference_Location

San Diego, CA

Print_ISBN

0-7803-0826-3

Type

conf

DOI

10.1109/CICC.1993.590695

Filename

590695