A 2.4-ns, 16-bit, 0.5-μm CMOS arithmetic logic unit for microprogrammable video signal processor LSIs

Author

Suzuki, Kazumasa ; Yamashina, Masakazu ; Goto, Junichi ; Inoue, Toshiaki ; Koseki, Youichi ; Horiuchi, Tadahiko ; Hamatake, Nobuhisa ; Kumagai, Kouichi ; Enomoto, Tadayoshi ; Yamada, Hiroyoshi

Author_Institution

NEC Corp., Kanagawa, Japan

fYear

1993

fDate

9-12 May 1993

Abstract

A 16-b arithmetic logic unit (ALU) has been developed for achieving high-speed microprogrammable video signal processor LSIs. The ALU employs a parallel architecture with newly developed high-speed circuit operations, including highly parallel addition, operand look-ahead overflow detection, and carry select zero-flag detection. The unit contains 6,272 transistors in a 1.50 mm × 1.09 mm die area using 0.5-μm CMOS process technology, and 2.4-ns ALU operations have been successfully achieved

Keywords

adders; 0.5 micron; 16 bit; 2.4 ns; CMOS arithmetic logic unit; carry select zero-flag detection; high-speed; highly parallel addition; microprogrammable video signal processor LSIs; operand look-ahead overflow detection; parallel architecture; Adders; Arithmetic; Automatic voltage control; CMOS logic circuits; Detectors; Hardware; Multiplexing; Parallel architectures; Signal detection; Signal generators;

fLanguage

English

Publisher

ieee

Conference_Titel

Custom Integrated Circuits Conference, 1993., Proceedings of the IEEE 1993

Conference_Location

San Diego, CA

Print_ISBN

0-7803-0826-3

Type

conf

DOI

10.1109/CICC.1993.590700

Filename

590700