An outline font rendering processor with an embedded RISC CPU for high-speed hint processing

Author

Kawata, Tetsuro ; Kawauchi, Kenichi ; Miyakawa, Nobuaki ; Kawazome, Ichiro ; Yasumatsu, Hiromi ; Haga, Susumu ; Takenaka, Masaya

Author_Institution

Fuji Xerox Co., Ltd., Kanagawa, Japan

fYear

1993

fDate

9-12 May 1993

Abstract

An outline font rendering processor which has a RISC (reduced instruction set computer) CPU (central processing unit) embedded on it has been developed. It unburdens the host CPU of whole font rendering, including hint processing. The chip consists of four functional units and operates on subprocesses of rendering concurrently and/or in a pipelined manner. The performances were measured using an Sbus evaluation board, and they are compared with those of software on the Sparc Station 2 and Sun4/110. Speed-ups ranging from a factor of 7 to a factor of 42 are shown. The rendering capability of the chip is equivalent to 50 and 30 page/min for English and Japanese, respectively. The chip was fabricated with a CMOS 0.8-μm process

Keywords

rendering (computer graphics); CMOS; Sbus evaluation board; digital differential unit; embedded RISC CPU; functional units; high-speed hint processing; outline font rendering processor; pipelined; rendering capability; CMOS process; Differential equations; Filling; Graphics; High speed integrated circuits; Performance evaluation; Printers; Reduced instruction set computing; Semiconductor device measurement; Software performance;

fLanguage

English

Publisher

ieee

Conference_Titel

Custom Integrated Circuits Conference, 1993., Proceedings of the IEEE 1993

Conference_Location

San Diego, CA

Print_ISBN

0-7803-0826-3

Type

conf

DOI

10.1109/CICC.1993.590701

Filename

590701