Investigation of area and speed trade-offs in FPGA implementation of an image correlation algorithm

Author

Kincses, Z. ; Vörösházi, Zs ; Nagy, Z. ; Szolgay, P. ; Laviniu, T. ; Gacsádi, A.

Author_Institution

Inst. of Inf., Univ. of Szeged, Szeged, Hungary

fYear

2012

fDate

29-31 Aug. 2012

Firstpage

1

Lastpage

5

Abstract

In this paper an image correlation algorithm is implemented on FPGA architecture for assisted movements of visually impaired persons or automotive driving systems. Taking into account the limitations of FPGA devices and the special requirements of the correlation based image matching algorithm a semi-parallel approach is proposed. This provides an optimal tradeoff between area and speed of the implemented algorithm. Several key issues are investigated and discussed related to the speed and area.

Keywords

automobiles; computer architecture; field programmable gate arrays; handicapped aids; image matching; parallel processing; traffic engineering computing; FPGA architecture; FPGA implementation; area tradeoffs; automotive driving systems; image correlation algorithm; image matching algorithm; semiparallel approach; speed tradeoffs; visually impaired persons; Arrays; Correlation; Correlators; Kernel; Shift registers;

fLanguage

English

Publisher

ieee

Conference_Titel

Cellular Nanoscale Networks and Their Applications (CNNA), 2012 13th International Workshop on

Conference_Location

Turin

ISSN

2165-0160

Print_ISBN

978-1-4673-0287-6

Type

conf

DOI

10.1109/CNNA.2012.6331455

Filename

6331455