Title :
SYSCHECK: A user-programmable mixed-mode verification tool
Author :
Hinners, M. ; Meixenberger, C. ; Astier, L. ; Degrauwe, M.
Author_Institution :
Centre Suisse d´´Electron. et de Microtechnique, Neuchatel, Switzerland
Abstract :
A user-programmable verification tool for debugging mixed-mode IC and PCB (printed circuit board) systems has been developed. Using this tool, the designer can define checking rules regarding block properties, pin properties, and interconnections. Rule definition is performed through a `zero-coding´ interface. Advantages include reduced simulation time and enhanced design security. This tool has been fully integrated into a schematic capture tool, showing the feasibility of a direct coupling between such a system debugger and the design environment. A block design for a phase locked loop is considered as an example
Keywords :
mixed analogue-digital integrated circuits; SYSCHECK; block properties; debugging; design security; interconnections; mixed-mode IC; mixed-mode verification tool; phase locked loop; pin properties; printed circuit board; reduced simulation time; rule definition; schematic capture tool; user-programmable; zero coding interface; Central Processing Unit; Circuit simulation; Clocks; Debugging; Design methodology; Digital circuits; Digital systems; Integrated circuit interconnections; Phase detection; Security;
Conference_Titel :
Custom Integrated Circuits Conference, 1993., Proceedings of the IEEE 1993
Conference_Location :
San Diego, CA
Print_ISBN :
0-7803-0826-3
DOI :
10.1109/CICC.1993.590709
