Cost, power, and parallelism in speech signal processing

Historically, it has been shown how applying huge numbers of transistors to a problem can reduce the cost of a system (as in the use of a digital signal processing chip instead of a few inductors and capacitors to implement a filter). It is noted that, in the age of portable products, one should think in terms of applying huge numbers of transistors to reduce the size and weight of the battery. The examples surveyed in this tutorial support the idea of using parallelism of slow processing units as a power-saving alternative to the single fast central processor that characterizes many of today´s desktop and portable products. A recent emphasis on the power problem within the VLSI signal processing community has led to an understanding of how parallelism can significantly reduce the cost of a system by greatly reducing clock speed, supply voltage, and power consumption, even though at the expense of silicon area and other measures of efficiency. Several different kinds and degrees of parallelism, including massive analog parallelism, should be considered in planning to reduce the total cost of speech signal processors