Automatic fault extraction and simulation of layout realistic faults for integrated analogue circuits

Author

Sebeke, C. ; Teixeira, J.P. ; Ohletz, M.J.

Author_Institution

Lab. fur Informationstechnol., Hannover Univ., Germany

fYear

1995

fDate

6-9 Mar 1995

Firstpage

464

Lastpage

468

Abstract

A comprehensive tool has been implemented for the comparison of different test preparation techniques and target faults. It comprises of the realistic fault characterisation program LIFT that can extract sets of various faults from a given analogue or mixed-signal circuit layout and the automatic analogue fault simulation program AnaFAULT which can handle arbitrary catastrophic and parametric faults. For a fabricated integrated VCO circuit the capabilities of the tool are demonstrated and simulation results are presented

Keywords

analogue integrated circuits; circuit analysis computing; fault diagnosis; integrated circuit layout; integrated circuit testing; mixed analogue-digital integrated circuits; voltage-controlled oscillators; AnaFAUL; LIFT; VCO; automatic analogue fault simulation program; catastrophic faults; circuit layout; integrated analogue circuits; mixed-signal circuit; parametric faults; realistic fault characterisation program; simulation; test preparation; Automatic testing; Circuit faults; Circuit simulation; Circuit testing; Circuit topology; Design automation; Laboratories; Manufacturing; Process design; Voltage-controlled oscillators;

fLanguage

English

Publisher

ieee

Conference_Titel

European Design and Test Conference, 1995. ED&TC 1995, Proceedings.

Conference_Location

Paris

Print_ISBN

0-8186-7039-8

Type

conf

DOI

10.1109/EDTC.1995.470319

Filename

470319