An FPGA based approach for the enhancement of COTS switch ASICs with real-time Ethernet functions

This paper presents an approach for the enhancement of standard switch ASICs with real-time Ethernet functions. Whereas a standard switch ASIC provides sophisticated mechanisms for switching of non real-time frames, an attached FPGA implements cut-through switching of real-time frames. The proposed FPGA architecture supports configuration of port numbers, bandwidth reservation for real-time frames and utilizes flow-control mechanisms of the ASIC in order to keep frame buffer sizes low. Mapping exemplary RTE extensions of PROFINET IRT onto a Xilinx Spartan 6 FPGA demonstrates the capability of providing band-width reservation and cut-through-forwarding of real-time frames. Therefore, the approach benefits from the innovations made by the switch manufacturers, whereas only a small amount of functions has to be mapped onto an FPGA.