Optimum stacked layout for analog CMOS ICs

A rigorous and efficient technique is presented for module generation in a maximally stacked layout paradigm for CMOS analog integrated circuits. Analog constraints on symmetry and matching provide a key for heuristics, substantially reducing the computational complexity of robust graph algorithms. The solution found minimizes a cost function accounting for parasitic control and routability considerations. Combined with sensitivity analysis and automatic constraint generation, this algorithm provides a suitable performance-driven approach to analog layout module generation. Examples are reported showing the effectiveness of this approach