A method for testability analysis and BIST insertion at the RTL

The goal of this research is to provide a means for BIST and circular BIST analysis and evaluation at the register transfer level (RTL). RTL circuits consist of interconnections of registers, functional units (ALUs), multiplexers and buses. The analysis is done via two metrics that measure the effectiveness with which an individual register in the circuit generates test patterns, the entropy-based randomness and expected state coverage. The testability metrics are computed by means of a Markov chain model that takes as input the RTL circuit description, and provides analytical values for the probability distribution of the state of each register in the circuit. The Markov model works by partitioning the circuit into small pieces, each containing the information necessary to analyze a single register. It then models each register separately as the register moves from state to state. A wide variety of BIST methodologies, including conventional, MISR-based, and circular BIST, can be modeled with this technique