Title :
HCNC: High Capacity Netlist Compare
Author_Institution :
Aiken Computation Lab., Harvard Univ., Cambridge, MA, USA
Abstract :
The author describes HCNC (High Capacity Netlist Compare), a technique for netlist comparison that uses the natural hierarchy of the transistor circuit to significantly increase the capacity of traditional netlist comparison algorithms. Since the natural hierarchy of the circuit is used, HCNC does not require hierarchical information from the user. HCNC also has some desirable properties for error recovery. Results from the network comparison of several large industrial circuits shall show the viability of this algorithm
Keywords :
circuit layout CAD; HCNC algorithm; High Capacity Netlist Compare; VLSI layout verification; coloring algorithm; error recovery; large industrial circuits; netlist comparison; Abstracts; Assembly; Circuit synthesis; Error correction; Iterative algorithms; Laboratories; Manufacturing; Network synthesis; Process design; Registers;
Conference_Titel :
Custom Integrated Circuits Conference, 1993., Proceedings of the IEEE 1993
Conference_Location :
San Diego, CA
Print_ISBN :
0-7803-0826-3
DOI :
10.1109/CICC.1993.590742
